Electrical power for an integrated circuit (IC) is typically supplied by one or more direct current (battery) power sources, such as a pulse width modulation (PWM)-based, DC—DC converter. This type of converter contains a PWM signal generator that supplies a synchronous PWM signal to a switching circuit driver. The switching circuit drive, in turn, controls the on-time and off-time of electronic power switching devices (such as a pair of FETs connected between a pair of power supply rails). A common node between the two FETs is coupled through an inductor to a load reservoir capacitor, with the connection between the inductor and the capacitor serving as an output node from which a desired (regulated) DC output voltage is applied to the load.
The pulse width modulator (PWM) circuit itself is typically implemented using a comparator which compares an output voltage from a control amplifier with a ramp waveform signal. The comparator output has a first state when the output voltage of the control amplifier is greater than the ramp waveform, and a second state when the voltage level of the ramp waveform has a value greater than the output voltage of the control amplifier. Thus, the duty cycle of the PWM waveform may be controlled by the output voltage of the control amplifier.
The ramp waveform signal itself may be generated by means of a feed-forward oscillator of the type diagrammatically illustrated in FIG. 1, wherein the peak-to-valley of the ramp voltage is made proportional to an input voltage Vin. In the circuit of FIG. 1, the input voltage Vin is coupled to a voltage divider comprised of a first resistor 11 having a resistor value R11=(N−1)R and a second resistor 12 having a resistor value R12=R coupled in series between Vin and ground (GND). The common connection 13 of resistors 11 and 12 supplies a voltage Vamplitude or Va. Owing to the values of resistors 11 and 12, Va is proportional to the input voltage Vin by a fraction 1/N; namely, Va=Vin/N.
This fractional voltage Vin/N is summed in an adder 20 with a voltage Vvalley that is supplied as a reference ramp floor or lower voltage input to the oscillator, to produce a peak voltage value Vpeak=Vin/N+Vvalley. The peak voltage Vpeak is coupled to a high side terminal H of a controlled switch 30, a common terminal 31 of which is coupled to a ramp output terminal 40. A capacitor C is coupled between the ramp output terminal 40 and ground. A low side terminal L of switch 30 is coupled to a current sink 50, the current through which is controlled by a phase locked loop (PLL) 60, which has a relatively low bandwidth (e.g., on the order of 3 KHz) to satisfy the linearity requirements of the ramp.
A variable switch connection 32 of switch 30 is alternately coupled between its common terminal 31 and the H and L terminals, in accordance with a reference clock signal REF CLOCK shown at 201 in the timing diagram of FIG. 2, which varies between high and low states, and serves as the reference clock signal for the PLL 60. When the REF CLOCK 201 is high, the variable switch connection 32 is coupled to receive the peak voltage Vpeak at the high side terminal H of switch 30; when the REF CLOCK 201 is low, variable switch connection 32 is coupled to terminal L and current sink 50.
The voltage Vvalley is further applied to a first (+) input 71 of a comparator 70, a second (−) input 72 of which is coupled to the ramp output terminal 40. The output 73 of comparator 70, which is coupled to the PLL 60, has a first state as long the voltage at its second input 72 is greater than that applied to its first input 71, and changes to a second state when the voltage at its second input drops below the voltage applied to its first input. Thus, comparator 70 produces an edge or transition in response to the voltage at the ramp output terminal 40 reaching the valley voltage.
Operation of the feed-forward oscillator of FIG. 1 may be understood by reference to the timing diagram of FIG. 2. Assuming a steady state operation for a first interval 81 of the input voltage Vin, then during the interval 201 that the REF CLOCK 200 is high, the variable switch connection 32 will be coupled to receive the peak voltage Vpeak at the high side terminal H, as pointed out above. As shown by the increasing excursion 211 of ramp waveform 210, this causes capacitor C to be rapidly charged to the value of the peak voltage Vpeak which, as noted earlier, equals the sum of the valley voltage Vvalley and a (1/N) fraction of the input voltage Vin.
During the succeeding low portion 202 of the REF CLOCK cycle 200, the variable switch connection 32 is coupled to the current sink 50, discharging the capacitor C. Ideally, the discharge current drawn from capacitor C by current sink 50 will be such as to cause the decreasing portion 212 of the ramp voltage 210 at terminal 40 to reach the level of the voltage Vvalley in time coincidence with the low-to-high transition in the REF CLOCK signal 200. If the ramp voltage 210 reaches the level of the voltage Vvalley ahead of the low-to-high transition in the REF CLOCK signal 200, the current being drawn by the current sink is too large, and the output of the PLL will cause a reduction in the discharge current drawn by current sink 50. Conversely, if the ramp voltage 210 reaches the level of the voltage Vvalley subsequent to the low to high transition in the REF CLOCK signal 200, the current being drawn by the current sink is too small, and the output of the PLL will cause the current drawn by sink 50 to increase.
As can be seen from the steady state portion 81 of the timing diagrams of FIG. 2, the output of the PLL 60 is stable and the current being drawn by current source 50 is such that the ramp voltage 210 reaches the level of the voltage Vvalley in time coincidence with the low-to-high transition in the REF CLOCK signal 200. During this first portion 81, the input voltage Vin is at some initial steady state input voltage Vin81 and, as shown at time t0, the ramp voltage 210 transitions from upper voltage Vpeak=(Vin81/N+Vvalley) to the valley voltage Vvalley in time coincidence with the low to high transition in the REF CLOCK signal 200.
At a time t1, which begins an interval 82, the input voltage Vin is shown as transitioning to a new input voltage Vin82, which is at a higher level than the initial steady state input voltage Vin81. As a consequence, during the next high portion 201 of the REF CLOCK signal, capacitor C is rapidly charged as shown by rising slope ramp portion 211A to a new value of the peak voltage Vpeak=Vin82/N+Vvalley. During the succeeding low portion 202 of the REF CLOCK cycle 200, with the variable switch connection 32 coupled to the current sink 50, capacitor C begins discharging through the current source 50, as shown by the decreasing slope portion 212A. Due to the relatively low bandwidth of the PLL, however, several cycles of the REF CLOCK signal 200 are required for the output of the PLL to adjust the magnitude of the current sink 50, so that the capacitor will be discharged from its new peak voltage (Vin82/N+Vvalley) back down to the Valley voltage (Vvalley) during a single REF CLOCK cycle. This means that during a PLL adaptation period 83, the ramp voltage will be undesirably distorted. This, in turn, negatively impacts the operation of the DC—DC converter in which the oscillator is employed.